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fm21ld16 2-mbit (128 k 16) f-ram memory cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-86192 rev. *b revised march 11, 2014 2-mbit (128 k 16) f-ram memory features 2-mbit ferroelectric random a ccess memory (f-ram) logically organized as 128 k 16 ? configurable as 256 k 8 using ub and lb ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see the data retention and endurance table) ? nodelay? writes ? page mode operatio n to 30-ns cycle time ? advanced high-reliability ferroelectric process sram compatible ? industry-standard 128 k 16 sram pinout ? 60-ns access time, 110-ns cycle time advanced features ? software-programmable block write-protect superior to battery-backed sram modules ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration low power consumption ? active current 8 ma (typ) ? standby current 90 ? a (typ) low-voltage operation: v dd = 2.7 v to 3.6 v industrial temperature: ?40 ? c to +85 ? c 48-ball fine-pitch ball grid array (fbga) package pin compatible with fm22ld16 (4-mbit) and fm23mld16 (8-mbit) restriction of hazardous substances (rohs) compliant functional overview the fm21ld16 is a 128 k 16 nonvolatile memory that reads and writes similar to a standard sram. a ferroelectric random access memory or f-ram is nonvolatile, which means that data is retained after power is removed. it provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed sram (bbsram). fast write timing and high write endurance make the f-ram superior to other types of memory. the fm21ld16 operation is simila r to that of other ram devices and therefore, it can be used as a drop-in replacement for a standard sram in a system. re ad and write cycles may be triggered by ce or simply by changing the address. the f-ram memory is nonvolatile due to its unique ferroelectric memory process. these features make the fm21ld16 ideal for nonvolatile memory applications requiring frequent or rapid writes. the fm21ld16 includes a low voltage monitor that blocks access to the memory array when v dd drops below v dd min. the memory is protected against an inadvertent access and data corruption under this condition. the device also features software-controlled write prot ection. the memory array is divided into 8 uniform blocks, each of which can be individually write protected. the device is available in a 48-ball fbga package. device speci- fications are guaranteed over the industrial temperature range ?40 c to +85 c. address latch & write protect ce control logic we block & row decoder a i/o latch & bus driver oe dq 16 k x 16 block 16 k x 16 block 16 k x 16 block 16 k x 16 block 16 k x 16 block 16 k x 16 block 16 k x 16 block 16 k x 16 block . . . column decoder . . . ub, lb 16-2 a 1-0 15-0 a 16-0 logic block diagram not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 2 of 22 contents pinout ................................................................................ 3 pin definitions .................................................................. 3 device operation .............................................................. 4 memory operation....................................................... 4 read operation ........................................................... 4 write operation ........................................................... 4 page mode operation ................................................. 4 pre-charge operation.................................................. 4 software write protect ................................................ 4 software write-protect timing .................................... 7 sram drop-in replacement....................................... 8 maximum ratings............................................................. 9 operating range............................................................... 9 dc electrical characteristics .......................................... 9 data retention and endurance ....................................... 9 capacitance .................................................................... 10 thermal resistance........................................................ 10 ac test conditions ........................................................ 10 ac switching characteristics ....................................... 11 sram read cycle .................................................... 11 sram write cycle..................................................... 12 power cycle and sleep mode timing ........................... 16 functional truth table................................................... 17 byte select truth table.................................................. 17 ordering information...................................................... 18 ordering code definitions ...... ................................... 18 package diagram............................................................ 19 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design supp ort............. .......... 22 products .................................................................... 22 psoc? solutions ...................................................... 22 cypress developer community................................. 22 technical support .................. ................................... 22 not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 3 of 22 pinout figure 1. 48-ball fbga pinout pin definitions pin name i/o type description a 16 ?a 0 input address inputs : the 17 address lines select one of 128k words in the f-ram array. the lowest two address lines a 1 ?a 0 may be used for page mode read and write operations. dq 15 ?dq 0 input/output data i/o lines : 16-bit bidirectional data bus for accessing the f-ram array. we input write enable : a write cycle begins when we is asserted. the rising edge causes the fm21ld16 to write the data on the dq bus to t he f-ram array. the falling edge of we latches a new column address for page mode write cycles. ce input chip enable : the device is selected and a new memory access begins on the falling edge of ce . the entire address is latched internally at this point. subsequent changes to the a 1 ?a 0 address inputs allow page mode operation. oe input output enable : when oe is low, the fm21ld16 drives the da ta bus when the valid read data is available. deasserting oe high tristates the dq pins. ub input upper byte select : enables dq 15 ?dq 8 pins during reads and writes . these pins are hi-z if ub is high. if the user does not perform byte writes and the device is not configured as a 256 k 8, the ub and lb pins may be tied to ground. lb input lower byte select : enables dq 7 ?dq 0 pins during reads and writes. these pins are hi-z if lb is high. if the user does not perform byte writes and the device is not configured as a 256 k 8, the ub and lb pins may be tied to ground. v ss ground ground for the device. must be connected to the ground of the system. v dd power supply power supply input to the device. nc no connect no connect. this pin is not connected to the die. we v dd a 11 a 10 nc a 6 a 0 a 3 ce dq 10 dq 8 dq 9 a 4 a 5 dq 13 dq 12 dq 14 dq 15 v ss a 9 a 8 oe v ss a 7 dq 0 ub nc nc a 2 a 1 lb v dd dq 2 dq 1 dq 3 dq 4 dq 5 dq 6 dq 7 a 15 a 14 a 13 a 12 nc 3 2 6 5 4 1 d e b a c f g h nc nc dq 11 (not to scale) top view ( 16) a 16 not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 4 of 22 device operation the fm21ld16 is a word wide f-ram memory logically organized as 131,072 16 and accessed using an industry-standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers page mode operation, which provides high-speed access to addresses within a page (row). access to a different page requires that either ce transitions low or the upper address (a 16 ?a 2 ) changes. see the functional truth table on page 17 for a complete description of read and write modes. memory operation users access 131,072 memory locations, each with 16 data bits through a parallel interface. the f-ram array is organized as eight blocks, each having 4096 rows. each row has four column locations, which allow fast access in page mode operation. when an initial address is latched by the falling edge of ce , subsequent column locations may be accessed without the need to toggle ce . when ce is deasserted high, a pre-charge operation begins. writes occur immediately at the end of the access with no delay. the we pin must be toggled for each write operation. the write data is st ored in the nonvolatile memory array immediately, which is a feature unique to f-ram called nodelay writes. read operation a read operation begins on the falling edge of ce . the falling edge of ce causes the address to be latched and starts a memory read cycle if we is high. data becomes available on the bus after the access time is met. when the address is latched and the access completed, a new access to a random location (different row) may begin while ce is still low. the minimum cycle time for random addresses is t rc . note that unlike srams, the fm21ld16's ce -initiated access time is faster than the address access time. the fm21ld16 will drive the data bus when oe and at least one of the byte enables (ub , lb ) is asserted low. the upper data byte is driven when ub is low, and the lower data byte is driven when lb is low. if oe is asserted after th e memory access time is met, the data bus will be driven with valid data. if oe is asserted before completing the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating tran sients caused by invalid data being driven to the bus. when oe is deasserted high, the data bus will remain in a hi-z state. write operation in the fm21ld16, writes occur in the same interval as reads. the fm21ld16 supports both ce and we controlled write cycles. in both cases, the address a 16 ?a 2 is latched on the falling edge of ce . in a ce -controlled write, the we signal is asserted before beginning the memory cycle. that is, we is low when ce falls. in this case, the device begins the memory cycle as a write. the fm21ld16 will not drive the data bus regardless of the state of oe as long as we is low. input data must be valid when ce is deasserted high. in a we -controlled write, the memory cycle begins on the falling edge of ce . the we signal falls some time later. therefore, th e memory cycle begins as a read. the data bus will be driven if oe is low; however, it will be hi-z when we is asserted low. the ce - and we -controlled write timing cases are shown in the page 14 . write access to the array begins on the falling edge of we after the memory cycle is initiated. th e write access terminates on the rising edge of we or ce , whichever comes first. a valid write operation requires the user to m eet the access time specification before deasserting we or ce . the data setup time indicates the interval during which data cannot change before the end of the write access (rising edge of we or ce ). unlike other nonvolatile memory te chnologies, there is no write delay with f-ram. because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the f-ram array is organized as eight blocks, each having 4096 rows. each row has four column-address locations. address inputs a 1 ?a 0 define the column address to be accessed. an access can start on any column address, and other column locations may be accessed without the need to toggle the ce pin. for fast access reads, after the first data byte is driven to the bus, the column address inputs a 1 ?a 0 may be changed to a new value. a new data byte is then driven to the dq pins no later than t aap , which is less than half the initial read access time. for fast access writes, the first write pulse defines the first write access. while ce is low, a subsequent write pulse along with a new column address provides a page mode write access. pre-charge operation the pre-charge operation is an in ternal condition in which the memory state is prepared for a new access. pre-charge is user-initiated by driving the ce signal high. it must remain high for at least the minimum pre-charge time, t pc . pre-charge is also activated by changing the upper addresses, a 16 ?a 2 . the current row is first closed before accessing the new row. the device automatically detects an upper order address change, which starts a pre-charge operation. the new address is latched and the new read data is valid within the t aa address access time; see figure 8 on page 13 . a similar sequence occurs for write cycles; see figure 13 on page 14 . the rate at which random addresses can be issued is t rc and t wc , respectively. software write protect the 128 k 16 address space is divided into eight sectors (blocks) of 16 k 16 each. each sector can be individually software write-protected and t he settings are nonvolatile. a unique address and command sequence invokes the write-protect mode. to modify write protection, th e system host must issue six read commands, three write commands, and a final read command. the specific sequence of read addresses must be provided to not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 5 of 22 access the write-protect mode. following the read address sequence, the host must write a data byte that specifies the desired protection state of each sector. for confirmation, the system must then write the comp lement of the protection byte immediately after the protection byte. any error that occurs including read addresses in the wrong order, issuing a seventh read address, or failing to complement the protection value will leave the write pr otection unchanged. the write-protect state machine monitors all addresses, taking no action until this particular read/write sequence occurs. during the address sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven to the data bus. any address that occurs out of sequence will cause the software protection state machine to start over. after the address sequence is completed, the next operation must be a write cycle. the lower data byte contains the write-protect settings. this value will not be written to the memory array, so the address is a don't-care. rather it will be held p ending the next cycle, which must be a write of the data comp lement to the protection settings. if the complement is correct, the write-protect settings will be adjusted. otherwise, the process is aborted and the address sequence starts over. the data value written after the correct six addresses will not be entered into the memory. the protection data byte consists of eight bits, each associated with the write-protect state of a sector. the data byte must be driven to the lower eight bits of the data bus, dq 7 - dq 0 . setting a bit to ?1? write-protects the corresponding sector; a ?0? enables writes for that sector. the following table shows the write-protect sectors with the corresp onding bit that contro ls the write-protect setting. the write-protect address sequence follows: 1. read address 12555h 2. read address 1daaah 3. read address 01333h 4. read address 0eccch 5. read address 000ffh 6. read address 1ff00h 7. write address 1daaah 8. write address 0eccch 9. write address 0ff00h 10.read address 00000h note if ce is low entering the sequence, then an address of 00000h must precede 12555h. the address sequence provides a secure way of modifying the protection. the write-protec t sequence has a one in 3 10 32 chance of randomly accessing exactly the first six addresses. the odds are further reduced by requiring three more write cycles, one that requires an exac t inversion of the data byte. figure 2 on page 6 shows a flow chart of the entire wr ite-protect operation. the write-protect sett ings are nonvolatile. the factory default: all blocks are unprotected. for example, the following sequence write-protects addresses from 0c000h to 13fffh (sectors 3 and 4): table 1. write protect sectors - 16 k 16 blocks sectors blocks sector 7 1ffffh?1c000h sector 6 1bfffh?18000h sector 5 17fffh?14000h sector 4 13fffh?10000h sector 3 0ffffh?0c000h sector 2 0bfffh?08000h sector 1 07fffh?04000h sector 0 03fffh?00000h address data read 12555h ? read 1daaah ? read 01333h ? read 0eccch ? read 000ffh ? read 1ff00h ? write 1daaah 18h; bits 3 and 4 = 1 write 0eccch e7h; complement of 18h write 0ff00h don?t care read 00000h not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 6 of 22 figure 2. write-protect state machine normal memory operation read 12555h? read 1daaah? any other operation read 01333h? read 0eccch? read 000ffh? read 1ff00h? hold data byte write 0eccch? write 0ff00h? y n n n n n y y y y n y write 1daaah? y y n read 00000h to enter new write protect settings n read 1aaaah to drive write protect settings write 0eccch? y read 00000h n y n change write protect settings read write protect settings sequence detector data complement? y n not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 7 of 22 software write-protect timing figure 3. sequence to set write-protect blocks [1] ce a we dq 12555 data data oe 01333 0eccc 000ff 1ff00 1daaa 0eccc 0ff00 00000 1daaa 16-0 15-0 figure 4. sequence to read write-protect settings [1] ce we 12555 x data oe 01333 0eccc 000ff 1ff00 0eccc 00000 1daaa t ce (read access time) 1aaaa a 16-0 dq 15-0 note 1. this sequence requires t as > 10 ns and address must be stable while ce is low. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 8 of 22 sram drop-in replacement the fm21ld16 is designed to be a drop-in replacement for standard asynchronous srams. the device does not require ce to toggle for each new address. ce may remain low for as long as 10 s. while ce is low, the device automatically detects address changes and a new access begins. it also allows page mode operation at speeds up to 33 mhz. figure 5 shows a pull-up resistor on ce , which will keep the pin high during power cycles, assuming the mcu / mpu pin tristates during the reset condition. the pull-up resistor value should be chosen to ensure the ce pin tracks v dd to a high enough value, so that the current drawn when ce is low is not an issue. a 10-k ? resistor draws 330 a when ce is low and v dd = 3.3 v note that if ce is tied to ground, the user must be sure we is not low at power-up or power-down events. if ce and we are both low during power cycles, da ta will be corrupted. figure 6 shows a pull-up resistor on we , which will keep the pin high during power cycles, assuming the mcu / mpu pin tristates during the reset condition.the pull-up resi stor value should be chosen to ensure the we pin tracks v dd to a high enough value, so that the current drawn when we is low is not an issue. a 10-k ? resistor draws 330 a when we is low and v dd = 3.3 v. note if ce is tied to ground, the user gives up the ability to perform the software write-protect sequence. for applications that require the lowest power consumption, the ce signal should be active (low) only during memory accesses. the fm21ld16 draws supply current while ce is low, even if addresses and control signals are static. while ce is high, the device draws no more than the maximum standby current, i sb . ce toggling low on every address access is perfectly acceptable in fm21ld16. the ub and lb byte select pins are active for both read and write cycles. they may be used to a llow the device to be wired as a 256 k 8 memory. the upper and lower data bytes can be tied together and controlled with the byte selects. individual byte enables or the next higher address line a 17 may be available from the system processor. figure 5. use of pull-up resistor on ce mcu / mpu ce we oe a 16-0 dq 15-0 fm21ld16 v dd figure 6. use of pull-up resistor on we figure 7. fm21ld16 wired as 256 k 8 mcu / mpu ce we oe a 16-0 dq 15-0 fm21ld16 v dd dq ce ub lb we oe 2-mbit f-ram fm21ld16 a 15-8 dq 7-0 d 7-0 16-0 a 17 a 16-0 not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 9 of 22 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +125 ?c maximum junction temperature ................................... 95 ?c supply voltage on v dd relative to v ss ........?1.0 v to + 4.5 v voltage applied to outputs in high z state .................................... ?0.5 v to v dd + 0.5 v input voltage .......... ?1.0 v to + 4.5 v and v in < v dd + 1.0 v transient voltage (< 20 ns) on any pin to ground potential ............ ..... ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ ............................ ..... +260 ?c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage human body model ( jedec std jesd22-a114-d ) ........ 2.5 kv charged device model ( jedec std jesd22-c101-c ) .... 800 v machine model ( jedec std jesd22-a115-a ) ................. 200 v latch-up current ................................................... > 140 ma operating range range ambient temperature (t a ) v dd industrial ?40 ? c to +85 ? c 2.7 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [2] max unit v dd power supply voltage 2.7 3.3 3.6 v i dd v dd supply current v dd = 3.6 v, ce cycling at min. cycle time. all inputs toggling at cmos levels (0.2 v or v dd ? 0.2 v), all dq pins unloaded. ?812ma i sb standby current v dd = 3.6 v, ce at v dd , all other pins are static and at cmos levels (0.2 v or v dd ? 0.2 v) t a = 25 ? c? 90 150 a t a = 85 ? c? ? 270 a i li input leakage current v in between v dd and v ss ??+ 1a i lo output leakage current v out between v dd and v ss ??+ 1a v ih input high voltage 2.2 ? v dd + 0.3 v v il input low voltage ? 0.3 ? 0.6 v v oh1 output high voltage i oh = ?1.0 ma 2.4 ? ? v v oh2 output high voltage i oh = ?100 a v dd ? 0.2 ? ? v v ol1 output low voltage i ol = 2.1 ma ? ? 0.4 v v ol2 output low voltage i ol = 100 a ? ? 0.2 v data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ?c 10 ? years t a = 75 ?c3 8 ? t a = 65 ?c1 5 1 ? nv c endurance over operating temperature 10 14 ? cycles note 2. typical values are at 25 c, v dd = v dd (typ). not 100% tested. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 10 of 22 ac test conditions input pulse levels ...................................................0 v to 3 v input rise and fall times (10%?90%) ........................... < 3 ns input and output timing reference levels ....................... 1.5 v output load capacitance ............................................... 30 pf capacitance parameter description test conditions max unit c i/o input/output capacitance (dq) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c in input capacitance 6pf thermal resistance parameter description test conditions 48-ball fbga unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 47 ?c/w ? jc thermal resistance (junction to case) 14 ?c/w not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 11 of 22 ac switching characteristics over the operating range parameters [3] description min max unit cypress parameter alt parameter sram read cycle t ce t ace chip enable access time ? 60 ns t rc ? read cycle time 110 ? ns t aa ? address access time ? 110 ns t oh t oha output hold time 20 ? ns t aap ? page mode address access time ? 25 ns t ohp ? page mode output hold time 5 ? ns t ca ? chip enable active time 60 10,000 ns t pc ? pre-charge time 50 ? ns t ba t bw ub , lb access time ? 20 ns t as t sa address setup time (to ce low) 0? ns t ah t ha address hold time (ce controlled) 60 ? ns t oe t doe output enable access time ? 15 ns t hz [4, 5] t hzce chip enable to output hi-z ? 10 ns t ohz [4, 5] t hzoe output enable high to output hi-z ? 10 ns t bhz [4, 5] t hzbe ub , lb highhigh to output hi-z ? 10 ns notes 3. test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 0 to 3 v, output loading of the specified i ol /i oh and load capacitance shown in ac test conditions on page 10 . 4. t hz , t ohz and t bhz are specified with a load capacitance of 5 pf. transition is measured when the outputs enter a high impedance state. 5. this parameter is characterized but not 100% tested. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 12 of 22 sram write cycle t wc t wc write cycle time 110 ? ns t ca ? chip enable active time 60 10,000 ns t cw t sce chip enable to write enable high 60 ? ns t pc ? pre-charge time 50 ? ns t pwc ? page mode write enable cycle time 25 ? ns t wp t pwe write enable pulse width 16 ? ns t as t sa address setup time (to ce low) 0 ? ns t asp ? page mode address setup time (to we low) 8 ? ns t ahp ? page mode address hold time (to we low) 15 ? ns t wlc t pwe write enable low to chip disabled 25 ? ns t blc t bw ub , lb low to chip disabled 25 ? ns t wla ? write enable low to a 16-2 change 25 ? ns t awh ? a 16-2 change to write enable high 110 ? ns t ds t sd data input setup time 14 ? ns t dh t hd data input hold time 0 ? ns t wz [6, 7] t hzwe write enable low to output hi-z ? 10 ns t wx [7] ? write enable high to output driven 10 ? ns t ws [8] ? write enable to ce low setup time 0 ? ns t wh [8] ? write enable to ce high hold time 0 ? ns ac switching characteristics (continued) over the operating range parameters [3] description min max unit cypress parameter alt parameter notes 6. t wz is specified with a load c apacitance of 5 pf. trans ition is measured when the ou tputs enter a high impedance state. 7. this parameter is characterized but not 100% tested. 8. the relationship between ce and we determines if a ce - or we -controlled write occurs. the parameters t ws and t wh are not tested. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 13 of 22 figure 8. read cycle timing 1 (ce low, oe low) figure 9. read cycle timing 2 (ce controlled) figure 10. page mode read cycle timing [9] a t rc t aa previous data valid data t oh valid data t rc t aa t oh dq 16-0 15-0 t as a dq t ce t hz t oe t oh t ohz ub / lb oe ce t ba t bhz t ca t pc t ah 16-0 15-0 t as t hz t aap t ohp ce a oe dq t ca a t oe t ce t ohz t pc data 0 data 1 data 2 col 0 col 1 col 2 16-2 1-0 15-0 note 9. although sequential column addressing is shown, it is not required not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 14 of 22 figure 11. write cycle timing 1 (we controlled) [10] figure 12. write cycle timing 2 (ce controlled) figure 13. write cycle timing 3 (ce low) [10] t wz t hz d in ce a we t ca t pc dq t wp t cw t as d out d out t ds t dh t wlc 15-0 16-0 t wx ce a we dq t as t dh t ds d in t ca t pc ub/lb t blc 15-0 16-0 t ws t wh t dh t wx d in a we dq t wc t wla t ds t awh d out d out t wz d in 16-0 15-0 note 10. oe (not shown) is low only to show the effect of we on dq pins. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 15 of 22 figure 14. page mode write cycle timing t asp t dh ce a we t ca t pc t cw col 0 col 1 data 0 col 2 t as t ds data 1 t wp data 2 oe t ahp t pwc t wlc 16-2 a 1-0 dq 15-0 note 11. ub and lb to show byte enable and byte masking cases. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 16 of 22 power cycle and sleep mode timing over the operating range parameter description min max unit t pu power-up (after v dd min. is reached) to first access time 450 ? s t pd last write (we high) to power down time 0 ? s t vr [12, 13] v dd power-up ramp rate 50 ? s/v t vf [12, 13] v dd power-down ramp rate 100 ? s/v figure 15. power cycle timing v dd t vf v dd min min v dd t vr t pu t pd access allowed notes 12. slope measured at any point on the v dd waveform. 13. cypress cannot test or characterize all v dd power ramp profiles. the behavior of the inte rnal circuits is difficult to predict when v dd is below the level of a transistor threshold voltage. cypress strongly recommends that v dd power up faster than 100 ms through the range of 0.4 v to 1.0 v. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 17 of 22 functional truth table ce we a 16-2 a 1-0 operation [14, 15] h x x x standby/idle l h h v v v v read l h no change change page mode read l h change v random read l l l v v v v ce -controlled write [15] l vvwe -controlled write [15, 16] l no change v page mode write [17] l x x x x x x starts pre-charge byte select truth table we oe lb ub operation [18] h h x x read; outputs disabled xhh h l h l read upper byte; hi-z lower byte l h read lower byte; hi-z upper byte l l read both bytes l x h l write upper byte; mask lower byte l h write lower byte; mask upper byte l l write both bytes notes 14. h = logic high, l = logic low, v = valid data, x = don't care, = toggle low, = toggle high. 15. for write cycles, data-in is latched on the rising edge of ce or we , whichever comes first. 16. we -controlled write cycle begins as a read cycle and then a 16-2 is latched. 17. addresses a 1-0 must remain stable for at least 10 ns during page mode operation. 18. the ub and lb pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256 k x 8. not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 18 of 22 ordering code definitions ordering information access time (ns) ordering code package diagram package type operating range 60 fm21ld16-60-bg 001-91158 48-ball fbga industrial FM21LD16-60-BGTR all the above parts are pb-free. option: blank = standard; tr = tape and reel package type: bg = 48-ball fbga access time: 60 ns i/o width: 16 voltage: 2.7 v to 3.6 v 2-mbit parallel f-ram cypress 21 fm ld 16 - 60 - bg tr not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 19 of 22 package diagram figure 16. 48-ball fbga (6 mm 8mm 1.2 mm) package outline, 001-91158 001-91158 ** not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 20 of 22 acronyms document conventions units of measure acronym description cpu central processing unit cmos complementary metal oxide semiconductor eia electronic industries alliance f-ram ferroelectric random access memory i/o input/output mcu microcontroller unit mpu microprocesser unit rohs restriction of hazardous substances r/w read and write sram static random access memory fbga fine-pitch ball grid array symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond m ? megaohm ns nanosecond ? ohm % percent pf picofarad v volt w watt not recommended for new designs
fm21ld16 document number: 001-86192 rev. *b page 21 of 22 document history page document title: fm21ld16, 2-mbit (128 k 16) f-ram memory document number: 001-86192 rev. ecn no. orig. of change submission date description of change ** 3912933 gvch 02/25/2013 new spec *a 4191946 gvch 11/14/2013 added watermark as ?not recommended for new designs.? *b 4274811 gvch 03/11/2014 converted to cypress standard format updated maximum ratings table - removed moisture sensitivity level (msl) - added junction temperature and latch up current updated data retention and endurance table added thermal resistance table removed package marking scheme (top mark) not recommended for new designs
document number: 001-86192 rev. *b revised march 11, 2014 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. fm21ld16 ? cypress semiconductor corporation, 2013-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support not recommended for new designs

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